1. Field of the Invention
The present invention relates to design technology on semiconductor integrated circuits. In particular, the present invention relates to a circuit designing system carrying out circuit designing processing based on a Test Point Insertion method and a circuit designing program.
2. Description of Related Art
In the field of semiconductor integrated circuits, there is a possibility of including defective products in the produced products at some percentages.
Accordingly, during the testing step, the defective products are removed and only good products are shipped. A yield rate at the occasion is called a yield factor. In order to improve the yield factor, it is necessary to clarify to improve the manufacturing process.
However, in the recent years, as the microtechnology is applied to semiconductor integrated circuits more, failure analysis is becoming more difficult. A reason thereof is that a failure analyzer is lacking resolution for the element size in the integrated circuit. For example, conventionally, as failure analyzer, optical failure analyzers such as an emission microscope, OBIRCH (Optical Beam Induced Resistance Change) apparatus and LVP (Laser Voltage Probe) have been used.
Such an optical failure analyzer uses long-wavelength light in the infra-red region and cannot obtain resolution not more than several tenths of a micron due to influence of the diffractive limit.
As an apparatus showing resolution higher than the above described optical failure analyzer, an electron beam (EB: Electron Beam) analyzer is known. In the case of an EB analyzer, electron beams are required to irradiate directly the wiring for analysis. However, in the current circumstances with increasing the number of wiring layers up to around eight layers, the wiring for analysis is not exposed in a lot of cases. Therefore, the EB analyzer is hardly applicable as well.
In addition, fault diagnosis guessing fault sites based on the result of an LSI test such as scan test is being widely used. However, in the case where the fault sites include a lot of equivalent faults, fault diagnosis cannot specify the true fault sites but a plurality of fault candidates will be extracted. In that case, it is still necessary to specify the true fault sites from a plurality of the fault candidates through measuring. For that purpose, it is necessary to use a Focused Ion Beam (FIB) apparatus to expose the wiring for measuring. And, after the wiring exposing processing is carried out, the EB analyzer is used to carry out measuring. However, a number of fault candidates occasionally increases to an extreme extent and, then, a significant number of steps will be required, resulting in an increase in work period required for fault analysis.
As one of Design For Testability (DFT) for simplifying such fault analysis, “Test Point Insertion” is known. According to TPI, in order to enhance testability (controlling performance and observing performance), a register called test point is inserted into a circuit for designing (see Patent Document 1 and Patent Document, for example).
The Patent Document 2 (Japanese Patent Application Laying Open 2005-313953) thereof describes the fault analysis simplifying technology formerly invented by the inventor of the present application. This document 2 is published as a United States patent application publication No. 2007/0113127. According to the fault analyzability technology (hereinafter to be referred to as “conventional system”) related to the preceding application, determination on the insertion position of the observation point (test point) will be devised to enable improvement in fault analyzability efficiently with further less observation points.
FIG. 1 exemplifies a circuit designing system related to an embodiment of a conventional system. That circuit design system comprises an input unit 1101, a storage 1103, a circuit layout unit 1105, a cell-to-cell distance extraction unit 1107, a fault candidate extraction unit 1109, a determination unit 1111, an observation point insertion unit 1113, a circuit wiring unit 1115 and an output unit 1117. The determination unit 1111 includes a fault analyzability assessment unit 1119 and an insertion positioning unit 1121. That circuit design system will be operated as follows.
At first, a NETLIST NET is input by the input unit 1101 and stored in the storage unit 1103. The circuit layout unit 1105 refers to that the NETLIST NET to arrange a cell group. Cell placement data ARR indicating the cell arrangement are stored in the storage unit 1103 and are output to the cell-to-cell distance extraction unit 1107. The cell-to-cell distance extraction unit 1107 makes reference to the placement data ARR to extract and calculate on cell-to-cell distance information. The cell-to-cell distance information DIS indicating the obtained cell-to-cell distance is output to the determination unit 1111.
The fault candidate extraction unit 1109 makes reference to the NETLIST NET to extract an equivalent fault class. The equivalent fault class consists of a plurality of fault candidates kept in equivalent relations, and measurement from outside cannot specify the fault sites in the equivalent fault class. For example, an equivalent fault class G1, G2 . . . GI (the suffix I being 1 or a larger integer) is assumed to be extracted. The respective equivalent fault class Gi (1=<i=<I) includes a plurality of equivalent fault nodes Ni1, Ni2 . . . NiJi (hereinafter to be referred to simply as node). The suffix Ji is the node number (fault candidate number) included in the equivalent fault class Gi. The fault candidate extraction unit 1109 outputs fault candidate data CAN indicting the extracted equivalent fault class Gi to the determination unit 1111.
Based on the fault candidate data CAN and the cell-to-cell distance data DIS, the determination unit 1111 determines “object node” where the observation points should be inserted from a plurality of nodes. Specifically, at first, the fault analyzability assessment unit 1119 of the determination unit 1111 calculates a parameter M derived by the following equation (1).
                              [Formula  1]                ⁢                                                                                      M        =                              ∑                          i              =              1                        I                    ⁢                                    J              i                        ·                          P              i                                                          (        1        )            
In the above described equation (1), the parameter Pi represents probability of a single stuck-at fault being included in the equivalent fault class Gi at an occasion when the relevant stuck-at fault takes place. In the circuit region with large cell-to-cell distance, wiring bringing the cells into connection will get long. Therefore probability of fault occurrence will become large. Accordingly, the probability Pi of the single stuck-at fault being included in the equivalent fault class Gi is given by the following equation (2), for example.
                              [Formula  2]                ⁢                                                                                                P          i                =                              1            2                    ·                                                    ∑                                  j                  =                  1                                                  J                  i                                            ⁢                              L                ij                                                    L              all                                                          (        2        )            
In the above described equation (2), the length Lall is a total length of all the equivalent fault classes G1 to GI or the entire wiring included in the entire circuit.
The length Lij is the respective wiring length of a plurality of nodes Ni1, Ni2 . . . NiJi included in a certain equivalent fault class Gi (the suffix j being an integer of not less than 1 and not more than Ji). Here, the fault analyzability assessment unit 1119 makes reference to cell-to-cell distance indicated by the cell-to-cell distance data DIS and thereby can guess the respective wiring length Lij.
As indicated in the above described equation (1), the parameter M is derived by the sum of parameter Ji·Pi for all the equivalent fault classes G1 to GI. That parameter M means an “average value” of the equivalent fault node number (fault candidate number) in the case where the single stuck-at fault has taken place in an arbitrary place in the circuit. In order to simplify fault analysis, only the average value of the fault candidate number at an occurrence of fault, that is, the parameter M has to be reduced. In that mean, the parameter M is referred to as “fault analyzability”. In order to improve fault analyzability M, that is, in order to reduce the parameter M, only the observation point has to be inserted into an appropriate position.
The insertion positioning unit 11221 of the determination unit 1111 determines such an observation point insertion position (object node) that improves the fault analyzability M “effectively”. For example, the insertion positioning unit 1121 determines an object node so as to reduce the parameter M to the maximum extent. For example, one equivalent fault class Gi including the maximum node number Ji has a large parameter Ji·Pi and contributes to the parameter M significantly. Accordingly, the object node is selected from equivalent fault nodes Ni1, Ni2 . . . NiJi included in that one equivalent fault class Gi and thereby the parameter M can be reduced significantly. Prioritized insertion of the observation point into the equivalent fault class including a lot of equivalent fault node will enable efficient improvement in the fault analyzability M.
Thus, the determination unit 1111 determines the object node where an observation point is to be inserted to generate observation point insertion position data PNT indicating the determined object node. The observation point insertion unit 1113 makes reference to the NETLIST NET and the observation point insertion position data PNT to insert at least one observation point into the object node. Thereby, the NETLIST NET is updated.
Corresponding with necessity, the above described process is repeated. The required process of observation point insertion process is finished and, then, the circuit wiring unit 1115 reads the NETLIST NET and the placement data ARR from the storage unit 1103. And, the circuit wiring unit 1115 carries out wiring process (routing) based on the NETLIST NET and the layout data ARR. Thereby, the layout data LAY indicating the layout of the circuit for design is prepared. The layout data LAY is output by the output unit 1117.
As described above, according to the conventional system, the object node is determined based on the node number Ji. For example, the probability of fault taking place in the equivalent fault class Gi including the maximum node number Ji may be the highest among all the equivalent fault classes. Accordingly, the object node is selected from one equivalent fault class Gi including the maximum node number Ji so that the observation point is inserted into that object node in a prioritized manner. Thereby, the average value (parameter M) of the fault candidate number in the case where the single stuck-at fault has taken place in an arbitrary place in the circuit is reduced efficiently. That is, improvement in the fault analyzability M is enabled at less insertion number of the observation point.    [Patent Document 1] Japanese Patent Application Laying Open 2005-135226    [Patent Document 2] Japanese Patent Application Laying Open 2005-313953
According to the conventional system, the “average value” of the fault candidate number at an occasion when the fault has taken place is reduced and thereby fault analysis is simplified. However, that does not necessarily means that the fault sites are not focused into one node through fault diagnosis. A reason thereof is that the observation points (test points) are preferentially inserted into the equivalent fault class with the large fault candidate number. Although the “average value” of the fault candidate number at a fault occurrence is reduced, the number of the fault candidate does not necessarily become one.
“Improvement in fault analyzability” can be contemplated from various points of views. From a certain point of view, the improvement in fault analyzability will mean to reduce the average value of the fault candidate number at a fault occurrence as in the conventional system. In addition, as another point of view, it is also contemplated to simplify fault site focusing so as to contribute to improvement in fault analyzability. At an occasion when a fault has taken place, such a technology is desired to increase the probability of enabling narrowing the fault candidate number down at least to a designated number.